A read-only memory (ROM) structure such as ROM 10 is shown in FIG. 1, where a set of rows or wordlines 11 cross columns or bitlines, e.g., two bitlines shown BL0, BL1. As shown in FIG. 1, in a typical ROM, an activation cell, typically comprising a transistor such as a MOSFET or similar semiconductor device 22, is triggered by a wordline signal to provide a stored bit value, e.g., logic level ‘1’ or logic level ‘0’, at the bitline. As shown in FIG. 1, two adjacent activation cells e.g., activation transistors 22, 24 that connect bitline BL1, share a common node, e.g., source node 20, which is connected to ground (GND). In this structure, cell programming is done by connecting or disconnecting the drain node from the bitline. To program an activation cell to ‘0’, the drain (or source) terminal 25 of transistor 22 is connected to the bitline, e.g., by a via or some other conductive connection. To program an activation cell to ‘1’, the drain (or source) is disconnected from the bitline such as terminal 27 of transistor 26. Bitlines are typically pre-charged to VDD, which can provide a logic level ‘1’ signal at bitline BL0 when transistor 26 is activated. During a read operation, one of the wordlines turns ON and bitline pre-charge is turned OFF. A corresponding cell programmed to ‘0’ will discharge the bitline. On the other hand, if the corresponding cell is programmed to ‘1’, it will not affect the bitline and the bitline will continue to stay at its pre-charged value. Alternatively the bitline could be pre-discharged to ground and the shared node between two adjacent activation cells could be a power supply voltage, e.g., referred to as “VDD”. In that configuration, to program an activation cell to ‘1’, the drain (or source) terminal is connected to the bitline and to program an activation cell to ‘0’, the drain (or source) is disconnected from the bitline. During a read operation in this configuration, one of the wordlines turns ON and the bitline pre-discharge is turned OFF. A cell programmed to ‘1’ will charge up the bitline. On the other hand, if a cell is programmed to ‘0’, it will not affect the bitline and the bitline will continue to stay at its pre-discharged value.
In the conventional ROM structure 10 of FIG. 1, loading on the bitline is greatly dependent upon the number of ‘1’s and ‘0’s on that bitline. For example if a bitline has 128 cells and all cells on that bitline are programmed to ‘0’, that bitline will have 128 bitline connections and the associated diffusion load. On the other hand if a 128-bit bitline has 127 ‘1’s and one ‘0’, that bitline will have only one bitline connection and will discharge significantly faster when reading that ‘0’ than the bitline that has 128 ‘0’s. The bitline loading and correspondingly the bitline discharge time will greatly vary depending upon the number of ‘1’s and ‘0’s (physical connections) on that bitline. Lightly loaded bitlines are more susceptible to noise than heavily loaded bitlines. This variation in the bitline loading can drive significant complexity in timing and adversely affect performance and power. There is a definite need to minimize the bitline load variation across all bitlines.
One prior art solution described in U.S. Pat. No. 5,917,224 entitled “Compact ROM Matrix” describes a ROM structure 30, shown in FIG. 2A, for improving the density of the ROM. In this prior art solution, both the drain and source connections are shared between adjacent transistors on a bitline. That is, given adjacent transistors 32, 34 connected to bitline BL0, as shown in FIGS. 2A and 2B, a cell is programmed to ‘0’ by connecting one side (e.g., the drain) of the transistor 32 to the bitline, and the other side 40 of the transistor 32 (e.g., source) to a separate GND line 15. To program a corresponding cell to ‘1’, both source and drain terminals are connected to a bitline, i.e., a BL/BL connection, or both source and drain terminals are connected to a GND line 15, i.e., a GND/GND connection. This allows the sharing of source and drain connections between adjacent transistors resulting in a dense ROM. For the bitline programming of the ROM structure as shown in FIG. 2A, bitline BL0 has three (3) physical bitline connections 29a, 29b and 39c and, bitline BL1 has two (2) connections 29e and 29f. 
FIG. 2B shows a ROM structure 30′ similar to the ROM structure 30 of FIG. 2A. However, for the same bitline programming of the ROM structure as shown in FIG. 2A, bitline BL0 has four (4) connections 39a, 39b, 39c and 39d and, bitline BL1 has five (5) connections 49a-49e. 
However, it is the case that the circuit structures 30 and 30′ do not completely address bitline load variation. For example, as shown in FIG. 3A, when a bitline has all activation devices programmed to logic ‘1’, the only solutions that would be possible are: 1) no bitline connections as shown as cell column 50 in FIG. 3A, or 2) both source/drain of all transistors connected to the bitline as shown as cell column 50′ in FIG. 3B. Neither case is desirable.
US Patents No. 2010/0177544 and No. 2011/0249481 offer some enhancements over U.S. Pat. No. 5,917,224. These two patents propose adding a ground line for every ROM cell column to improve bitline shielding and also describe a method for improving ROM performance by changing the width of the ROM cell device when the ROM is programmed. However those patents also do not address bitline load balancing.
It would be desirable to provide a method of designing the bitline cell architecture for bitline programming that would enable optimal bitline loading for any combination of ‘1’s and ‘0’s on the bitline.